Amiga 4000 Replica with Schematics

$5,170 of $5,000 goal

Raised by 118 people in 3 months
As many owners of the Amiga 4000 boards know they contain a battery and several electrolytic capacitors which when age and leak cause severe damage to the motherboard. The goal of this fundraiser is to have the original board converted to schematics and Gerber files. This will allow new boards to be manufactured. The schematics will allow future updates and changes to the design of the board for future enhancements or improvements. 

This work will be accomplished by Integrated Sensor Technologies, located in Goleta California ( www.isensortech.com) and will take 4 - 6 weeks for completion. Once complete the files will be released publicly and hosted on a site such as github. The project does not include any boards and is only for the funding of the engineer and the work required to complete the file conversion project. Any boards will have to be purchased by those requiring them from a PCB manufacturer on their own. 

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One more quick update on the 4000 Rev B project. The FINAL review is done and checks out. I have uploaded the new file in the layout folder at git hub. Also uploaded is a zip with Additional outputs included. These have been translated from the original PADS database so use them at your own peril.
The Altium file looks good. Supposedly Eagle will import an Accel ASCII database but my first try was not successful. The file does not look correct. Worst case, those that know what to do can import the Gerber and recreate the database from it. Eagle just does not have a good importer at this time.

I will not be supporting design changes in anything other than the PADS database. The Altium and Eagle outputs in the additional outputs zip is just something I have had done as a thank you. I do believe the free version of Altium called Circuit Works? will import the Altium data. This would be the best way to go for those looking to get a good alternative to PADS.
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This is it! This first views of the now completed A4000 Rev B layout! I'm going over it and will soon ask for feedback on this. Please remember this is in Mentor Graphics PADS and requires the viewer from them if you want to see it yourself. It's free from them. This is amazing work! The pcb database file is located in the layout folder at the Github here: https://github.com/Acill/A4000RevB
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One more update! I have asked the designer to update the silk to a modern corrected design. I have also mentioned about the few errors such as C433/443 reversed to be fixed which he has done. See the email below:

I have run a series of validation tests on the layout design and it now pass all integrity tests. These have to do with the database.
I am in the process of cleaning it up so it passes design rule tests now. I am targeting 8mil separation with 8-10mil signal traces. The power connections will have a minimum of 20mils unless it violates a pad entry. I have defined the inner layers and proceeding with internal trace routing and copper pour definition.
In the end it will look very similar or almost exactly as the original.

I have a question regarding the silkscreen. I can use the original or up date it to a normal configuration. The problem with the original is that it violates a rule.
That is, it is on some of the pads it overlaps other features. Let me know which way you want to proceed with the silkscreen.
I could also try and clean up the original.

Without the electrical comparison test or a board being fabricated and tested, I am 99.99% confident in the schematic. That will be the same for the layout when complete.
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More info from the PCB design firm we are working with. This is the email I received this evening. The new files are posted at the GitHub.

"This is the final schematic without the electrical comparison test.
I fix the flag problems and found a few other problems that I have also fixed. I have very high confidence in the schematic and netlist at this time.
Schematic matches the PDF which also now matches the PCB. There were some errors in the provided PCB.
There are 3 nets which are not connected, IO_CH_RDY, _LDS and _UDS.

I did not make any changes from the original design such as tying the unused logic gate inputs to ground.

FYI, this is a 4 layer board with mixed signal / planes for the inner layers. They originally used the internal layers to make some of the signal connections in addition to power and ground planes."
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Raised by 118 people in 3 months
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